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发布时间:2023-08-11来源:芯学长 0

But the open source processor architecture will need to find more support from the software dev community before it can rival x86 and ARM architectures in the data center: A wrap-up of RISC-V Summit in Barcelona.


Developers have grown up hearing ARM or x86 being the guts of PCs and servers, but an alternative architecture called RISC-V is emerging.


In the next few years, some companies will inevitably ship PCs and servers running on RISC-V processors. Those systems will likely run on Linux as Microsoft is not known to be developing a Windows OS for the architecture.


But there are big problems with the software ecosystem — the developer support is pitiful. RISC-V International, which is developing the chip architecture, talks more about hardware, with software a distant second in priorities.

但是软件生态系统存在很大的问题——开发人员的支持是可怜的。正在开发芯片架构的RISC-V International更多地谈论硬件,软件在优先级上遥遥领先。

Initial Support


Since its emergence close to a decade ago, RISC-V quickly gained the support of major chip makers, including Apple, which has put controllers in its Apple Silicon. About 10 billion chip cores based on RISC-V have shipped. Most recently, Meta announced an AI inferencing chip built on RISC-V architecture.

自近十年前出现以来,RISC-V迅速获得了主要芯片制造商的支持,包括苹果公司,苹果公司已将控制器置于其苹果硅中。基于RISC-V的芯片内核已经出货了大约10亿个。最近,Meta 宣布推出一款基于 RISC-V 架构的 AI 推理芯片。

The chip architecture is often called a hardware equivalent of Linux. It is a free chip technology built on a contributor culture and the ethos of open source, in which a community works together to develop and improve the product.


RISC-V is a free-to-license architecture, which means anyone can fork a version of the architecture into their own chip.


Chips with RISC-V can be compiled like Lego blocks — companies that take the base architecture, and top it off with proprietary hardware blocks that may include accelerators for AI, graphics, or security.

带有RISC-V的芯片可以像乐高积木一样编译 - 采用基本架构的公司,并使用专有硬件块进行编译,这些硬件模块可能包括用于AI,图形或安全的加速器。

“What was once an experiment, a prototype, is quickly moving into production,” said Calista Redmond, during a keynote at last month’s RISC-V Summit in Barcelona.

“曾经是一个实验,一个原型,正在迅速投入生产,”Calista Redmond在上个月在巴塞罗那举行的RISC-V峰会上发表主题演讲时说。

The structure of RISC-V makes it suitable for cloud native environments handling diverse applications and complex computing requirements.


The minimal base instructions are designed to quickly offload applications such as AI and analytics to accelerators like GPUs or specialized math processors, which excel at such tasks.

最小基本指令旨在将 AI 和分析等应用程序快速卸载到 GPU 或专用数学处理器等加速器,这些加速器擅长此类任务。

Chips from Intel and AMD are reaching their physical limits, and the flexibility of RISC-V provides a structure to move computing into the future.


For example, RISC-V provides a pathway for new hardware architectures such as sparse computing, which is being researched by the Intelligence Advanced Research Projects Activity, in which processing units are closer to the data in storage or memory.


The Barcelona Supercomputing Centre proposed the concept of merging CPU and memory in a RISC-V chip, which will reduce the memory bottleneck posed by machine-learning applications.


“What we want from it — it is actually to do memory-intensive operations close to memory, like memcpy,” said Umair Riaz, a researcher at BSC, referring to the C++ function to copy memory blocks. Riaz also referenced the spinlock function, and mentioned the CPU executing those in memory will be more efficient and faster.

“我们想要从中得到的 - 它实际上是在内存附近进行内存密集型操作,就像memcpy一样,”BSC的研究员Umair Riaz说,他指的是复制内存块的C++功能。Riaz还提到了自旋锁函数,并提到在内存中执行这些函数的CPU将更高效,更快。

“Executing functions locally you will eventually get performance and less [network] traffic because you are doing much more closer to memory,” Riaz said.


Writing applications for such complicated RISC-V chips may be a load for even the bravest programmers that want to code directly to the hardware. But Intel wants to provide the tooling needed for coders to start testing applications in simulated RISC-V environments.



Intel’s Codeplay software unit recently announced the OneAPI Construction Kit, which includes tools for developers to test code in a simulated RISC-V environment on x86 PCs.

英特尔的Codeplay软件部门最近发布了OneAPI构建套件,其中包括供开发人员在x86 PC上的模拟RISC-V环境中测试代码的工具。

The Construction Kit’s signature feature is support for SYCL — which allows coders to write and compile applications regardless of the hardware architecture — and Intel is taking the first steps to bring RISC-V support to the parallel-programming framework.

该构建套件的标志性功能是支持 SYCL,它允许编码人员编写和编译应用程序,而不管硬件架构如何,英特尔正在迈出第一步,将 RISC-V 支持引入并行编程框架。

The kit includes support for Intel’s DPC++/C++ Compiler, which allows C++ code to be recompiled for use across multiple hardware architectures.

该套件包括对英特尔 DPC++/C++ 编译器的支持,该编译器允许重新编译C++代码以跨多个硬件架构使用。

Developers can also test RISC-V code on Raspberry Pi-like developer boards or systems from companies such as Milk-V, and StarFive. Both companies offer high-performance 64-bit RISC-V systems with support for Linux.

开发人员还可以在类似Raspberry Pi的开发板或Milk-V和StarFive等公司的系统上测试RISC-V代码。两家公司都提供支持Linux的高性能64位RISC-V系统。

Support for Linux tools on RISC-V are tepid. Only a handful of packages are fully supported, and that includes Ubuntu OS, Gnu Toolchain, OpenvSwitch, Apache Nuttx, and Spidermonkey for Mozilla.

RISC-V上对Linux工具的支持不温不火。只有少数软件包完全支持,其中包括Ubuntu OS,Gnu Toolchain,OpenvSwitch,Apache Nuttx和Mozilla的Spidermonkey。

Many packages for RISC-V will work reasonably well, but are still not fully supported. For example, the RISC-V developer community in China reported that more than 80% of the packages in open source Fedora are now supported on RISC-V,


Some key packages, such as Pytorch, GCC, TensorFlow, and OpenJDK will work, but are not yet fully supported. Support for open source applications like LibreOffice and Firefox are being built up. Google is accelerating its support of AOSP (Android Open Source Project) on RISC-V, which will be a big part of the next architecture specification.


RISC-V server chip makers Esperanto Technologies and Ventana Micro Systems have announced server chips for cloud computing, but have not talked much about software support or programming models. Esperanto has ported Meta’s Open Pre-Trained Transformer model to its RISC-V server.

RISC-V服务器芯片制造商Esperanto Technologies和Ventana Micro Systems已经宣布了用于云计算的服务器芯片,但没有过多谈论软件支持或编程模型。Esperanto 已将 Meta 的开放预训练变压器模型移植到其 RISC-V 服务器上。

RISC-V International, which is developing the architectural spec, is trying to solve that problem with the establishment of the RISC-V Software Ecosystem, also called RISE, to create the underlying software tools and middleware for RISC-V systems. The initial backers include companies such as Google, Intel, Nvidia, Qualcomm, Samsung, and Ventana.


Mark Himelstein, chief technology officer RISC-V International, at the summit talked about RISC-V taking a page from the cultural roots of Linux culture, with contributors contributing to the shared interests.

RISC-V International首席技术官Mark Himelstein在峰会上谈到了RISC-V从Linux文化的文化根源出发,贡献者为共同的利益做出了贡献。

“That contributor culture means upstreaming on RISC-V and other communities where open source and open standards play a part,” Himelstein said, adding “that does not mean you are working on the pieces of the puzzle that are rapidly commoditizing.”


There is also no structure for hardware and software co-design that makes it easier for coders to use x86 and ARM systems. RISC-V first develops a hardware spec and Linux compatibility comes later. That is very different than Intel, which upstreams Linux drivers for a chip before it is released, which ensures the hardware is compatible with the latest build of the OS.

硬件和软件协同设计也没有结构,使编码人员更容易使用 x86 和 ARM 系统。RISC-V首先开发硬件规范,Linux兼容性稍后出现。这与英特尔非常不同,英特尔在芯片发布之前上游Linux驱动程序,确保硬件与最新版本的操作系统兼容。

China, Tho

(RISC-V’s software efforts also lack a force of nature like Linus Torvalds that can drive a project forward by sheer will. RISC-V also is not mainstream enough to attract an army of developers.)

RISC-V的软件工作也缺乏像Linus Torvalds那样的自然力量,这种力量可以通过纯粹的意志推动项目向前发展。RISC-V也不够主流,无法吸引大量开发人员。

But it is a different scene with China, which is adopting RISC-V on a massive scale to create homegrown chips and reduce its reliance on Western technology. Developers in China are rolling up their sleeves and contributing coding to stand-up RISC-V compatible operating systems for Linux.


Their motivation is simple — an engineering focus is driving China’s RISC-V initiative, not politics, and there is plenty of motivation for developers to build OS support, especially with the latest Western chip technology out of sight due to export restrictions.


Chinese companies are developing some of the most sophisticated RISC-V chips, and the community is adding support for more packages daily. Many of the core contributors to Fedora, Debian, Gentoo and Arch Linux, GNU toolchain, and Clang are in China.

中国公司正在开发一些最先进的RISC-V芯片,社区每天都在增加对更多封装的支持。Fedora、Debian、Gentoo 和 Arch Linux、GNU 工具链和 Clang 的许多核心贡献者都在中国。

The RISC-V community in China is also leading a grassroots effort to bring support for ROCm — which is AMD’s parallel-programming framework — to RISC-V processors. AMD did not respond to requests for comment on whether it was involved in porting ROCm to RISC-V.



About HS-2

HS-2 RISC-V通用主板是澎峰科技与合作伙伴共同研发的一款专为开发者设计的标准mATX主板,它预装了澎峰科技为RISC-V高性能服务器定制开发的软件包,包括各种标准bencmark、支持V扩展的GCC编译器、计算库、中间件以及多种典型服务器应用程序。

HS-2 RISC-V通用主板搭载了一颗国产RISC-V 64核处理器(SG2042)。SG2042是目前已量产的性能最高的RISC-V处理器,主要针对高性能计算领域需求设计,适用于科学计算、工程计算、AI计算、融合计算等大算力应用场景。



RISC-V Finds Its Foothold in a Rapidly Evolving Processor Ecosystem


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